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 HT49RA0/HT49CA0 Remote Type 8-Bit MCU with LCD
Technical Document
* Tools Information * FAQs * Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: 2.0V~3.6V * 8 bidirectional I/O lines and 8 input lines * Two external interrupt input * One 8-bit programmable timer/event counter * LCD driver with 212, 213 or 204 segments * 2K14 program memory * 968 data memory RAM * Real Time Clock (RTC) * 8-bit prescaler for RTC * One carrier output (1/2 or 1/3 duty) * Software LCD, RTC control * On-chip RC and 32768Hz crystal oscillator * Watchdog Timer * HALT function and wake-up feature reduce power
consumption
* 4-level subroutine nesting * Bit manipulation instruction * 14-bit table read instruction * Up to 1ms instruction cycle with 4MHz system clock * 63 powerful instructions * All instructions in 1 or 2 machine cycles * Low voltage reset/detector function * 52-pin QFP package
General Description
The HT49RA0/HT49CA0 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product applications. The mask version HT49CA0 is fully pin and functionally compatible with the OTP version HT49RA0 device. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, watchdog timer, HALT and wake-up functions, as well as low cost, enhance the versatility of this device to suit a wide range of application possibilities such as industrial control, consumer products, and particularly suitable for use in products such as infrared LCD remote controllers and various subsystem controllers. The HT49CA0 is under development and will be available soon.
Rev. 1.20
1
October 24, 2007
HT49RA0/HT49CA0
Block Diagram
In te rru p t C ir c u it P ro g ra m m e m o ry P ro g ra m C o u n te r STACK IN T C S Y S C L K /4 In s tr u c tio n R e g is te r F r e q u e n c y D iv id e r MP M U X DATA M e m o ry fS fS X
YS YS
TM RC TM R
M U
/4
R T C In te rru p t P B 2 /T M R L e v e l o r C a r r ie r C a r r ie r C o n tr o l P C 0 C o n tro l P C 0 /R E M
RTC In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n S h ifte r PA BP OSC4 OS RE VD VS OS S C1 SB D C3 L C D D r iv e r H ALT C O M 0~ COM2 C O M 3/ SEG 20 SEG 0~ SEG 19 E N /D IS ACC LCD M e m o ry PORT B PB PORT A MUX W DT STATUS T im e B a s e M U X
S Y S C L K /4 OSC3 OSC4
RTC
OSC
W DT OSC
PA0~PA7
P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R PB3~PB7
L V D /L V R
Pin Assignment
O O S S S EG EG EG SC SC VD SC RE PA PA PA PA PA D S 4 1 3 4 PA5 PA6 PA7 /IN T 0 /IN T 1 /T M R PB3 PB4 PB5 VSS /R E M PB6 PB7 1 2 3 4 5 6 7 8 10 11 12 13 14151617181920212223242526 9 H T 4 9 R A 0 /H T 4 9 C A 0 5 2 Q F P -A 52515049484746454443424140 3 2 1 0 0 1 2 39 38 37 36 35 34 33 32 31 30 29 28 27 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 4 5 6 7 8 9 10 11 12 13 14 15 3 O
PB0 PB1 PB2
PC0
SEG SEG SEG SEG COM COM COM COM C2 C1 V2 V1 VLC D 16 17 18 19 3 /S E G 2 0 2 1 0
Rev. 1.20
2
October 24, 2007
HT49RA0/HT49CA0
Pin Description
Pin Name PA0~PA7 PB0/INT0 PB1/INT1 PB2/TMR PB3~PB7 PC0/REM V1, V2, C1, C2 VLCD COM0~COM2 COM3/SEG20 SEG0~SEG11 SEG12~SEG19 OSC1 OSC3 OSC4 RES VSS VDD O O O I I O I 3/4 3/4 1/2, 1/3 or 1/4 Duty 3/4 I/O I/O Options 3/4 Description Bidirectional 8-bit input/output port with pull-high resistors. Each bit can be determined as NMOS output or Schmitt trigger input by software instructions. 8-bit Schmitt trigger input port with pull-high resistors. Eash bit can be configured as a wake-up input by code option. Pins PB0, PB1 and PB2 are pin-shared with INT0, INT1 and TMR respectively.
I
Wake-up
I/O I
Level or Carrier Level or carrier output pin Pull-high PC0 can be set as CMOS output pin or carrier output pin by code option. 3/4 Voltage pump LCD power supply VLCD should be larger than VDD for correct operation i.e. VLCD VDD. COM3/SEG20 can be set as a segment or as a common output driver for LCD panel by options. COM0~COM2 are output for LCD panel plate. LCD driver outputs for LCD panel segments.
SEG12~SEG19 LCD driver outputs for LCD panel segments. CMOS output SEG12~SEG19 can be optioned as logical outputs. RC OSC1 connect a resistor to GND for internal system clock. Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purpose. It cant be used as a system clock. No capacitor is built-in. If RTC is not selected as fs. OSC3,OSC4 should be left floating. Schmitt trigger reset input, active low. Negative power supply, ground Positive power supply
3/4
3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions Symbol VDD IDD ISTB1 ISTB2 Parameter VDD Operating Voltage Operating Current (RC OSC) Standby Current (*fS=T1) Standby Current (*fS=32.768kHz OSC) 3/4 3V 3V 3V Conditions 3/4 No load, fSYS=4MHz No load, system HALT, LCD off at HALT No load, system HALT, LCD On at HALT, C type 2.0 3/4 3/4 3/4 3/4 0.7 0.1 2.5 3.6 1.5 1 5 Min. Typ. Max.
Ta=25C Unit V mA mA mA
Rev. 1.20
3
October 24, 2007
HT49RA0/HT49CA0
Test Conditions Symbol ISTB3 VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 IOL2 IOH2 RPH VLVR VLVD VPOR RPOR Note: Parameter VDD Standby Current (*fS=WDT RC OSC) Input Low Voltage for I/O Ports, TMR, INT0 and INT1 Input High Voltage for I/O Ports, TMR, INT0 and INT1 Input Low Voltage (RES) Input High Voltage (RES) I/O Port & REM Sink Current I/O Port & REM Source Current LCD Common and Segment Current LCD Common and Segment Current Pull-high Resistance of I/O Ports Low Voltage Reset Voltage Low Voltage Detector Voltage VDD Start Voltage to Ensure Power-on Reset VDD Rise Rate to Ensure Power-on Reset 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3/4 3/4 3/4 3/4 Conditions No load, system HALT LCD On at HALT, C type 3/4 3/4 3/4 3/4 VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 4 -5 210 -80 100 2.0 2.2 3/4 0.035 2 3/4 3/4 3/4 3/4 8 -7 420 -160 150 2.1 2.3 3/4 3/4 5 0.3VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 200 2.2 2.4 100 3/4 mA V V V V mA mA mA mA kW V V mV V/ms Min. Typ. Max. Unit
* for the value of VA refer to the LCD driver section. tSYS=1/fSYS *fS please refer to WDT clock option
A.C. Characteristics
Test Conditions Symbol Parameter VDD fSYS fRTCOSC fTIMER System Clock RTC Frequency Timer I/P Frequency (TMR) 3/4 3/4 3V 3V 3/4 3/4 3/4 3/4 Conditions 2.0V~3.6V, 4MHz 3%, Temp.= 0C ~ 50C 3/4 3/4 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 0 45 1 0.25 3/4 1 4000 32768 3/4 90 3/4 1 1024 3/4 3/4 3/4 4000 180 3/4 2 3/4 3/4 Min. Typ. Max.
Ta=25C Unit
kHz Hz kHz ms ms ms *tSYS ms
tWDTOSC Watchdog Oscillator Period tRES tLVR tSST tINT Note: External Reset Low Pulse Width Low Voltage Width to Reset System Start-up Timer Period Interrupt Pulse Width *tSYS=1/fSYS
Rev. 1.20
4
October 24, 2007
HT49RA0/HT49CA0
Functional Description
Execution Flow The system clock is derived from RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is of 11 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 2048 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed with the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
T1 T2 T3 T4 T1 T2 T3 T4
S y s te m O S C 2 (R C
C lo c k o n ly ) PC
T1
T2
T3
T4
PC F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
PC+1
PC+2
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter Mode *10 Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter overflow Time Base Interrupt RTC Interrupt Skip Loading PCL Jump, Call Branch Return From Subroutine *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 0 0 0 0 0 0 *9 0 0 0 0 0 0 *8 0 0 0 0 0 0 *7 0 0 0 0 0 0 *6 0 0 0 0 0 0 *5 0 0 0 0 0 0 *4 0 0 0 0 1 1 *3 0 0 1 1 0 0 *2 0 1 0 1 0 1 *1 0 0 0 0 0 0 *0 0 0 0 0 0 0
Program Counter + 2 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: PCL bits
Rev. 1.20
5
October 24, 2007
HT49RA0/HT49CA0
When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory (ROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048 14 bits which are addressed by the program counter and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H * Location 014H
Location 014H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.
* Table location
Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.
* Location 004H
Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
* Location 008H
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining 2 bit is read as 0. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the users requirements.
000H 004H 008H 00C H 010H 014H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t 0 s u b r o u tin e E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e B a s e In te r r u p t R T C In te rru p t P ro g ra m ROM
Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H.
* Location 00CH
Location 00CH is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
100H 1FFH nFFH 700H 7FFH
Location 010H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 010H.
L o o k - u p ta b le ( 2 5 6 w o r d s )
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 6
Program Memory
Table Location Instruction(s) *10 TABRDC [m] TABRDL [m] P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *10~*0: Table location bits @7~@0: Table pointer bits P10~P8: Current program Counter bits
Rev. 1.20
6
October 24, 2007
HT49RA0/HT49CA0
Stack Register - STACK The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 4 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a commencement of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the program counter is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 4 return addresses are stored). Data Memory - RAM The data memory is divided into two functional group : special function registers (208) and general purpose data memory (968). Most of them are read/write, but some are read only. The unused space before 20H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 20H to 7FH, is used for data and control information under instruction command. The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 7-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H IN T C 1 LCD C G e n e ra l P u rp o s e D a ta M e m o ry (9 6 B y te s ) 7FH :U nused. R e a d a s 0 0 PC PCC PB PA In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R TM RC S p e c ia l P u r p o s e D a ta M e m o ry
RAM Mapping Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation but also changes the status register. 7 October 24, 2007
Rev. 1.20
HT49RA0/HT49CA0
Status Register - STATUS The status register (0AH) is of 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Interrupts The devices provides two external interrupts, one internal timer/event counter interrupts, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low or low to high or both transition of INT0 or INT1, and the related interrupt request flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts.
Bit No. 0
Label C
Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6, 7
AC Z OV PDF TO 3/4
Rev. 1.20
8
October 24, 2007
HT49RA0/HT49CA0
The internal Timer/Event Counter interrupt is initialized by setting the Timer/Event Counter interrupt request flag (TF;bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the TF bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (TF) is reset, and the EMI bit is cleared to disable further interrupts. The time base interrupt is initialized by setting the time base interrupt request flag (TBF;bit 4 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 10H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 5 of INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source External interrupt 0 External interrupt 1 Timer/Event Counter overflow Time base interrupt Real time clock interrupt Priority 1 2 3 4 5 Vector 04H 08H 0CH 10H 14H
The EMI, EEI0, EEI1, ETI, ETBI and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction.
Bit No. 0 1 2 3 4 5 6 7
Label EMI EEI0 EEI1 ETI EIF0 EIF1 TF 3/4
Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt 0 (1=enabled; 0=disabled) Controls the external interrupt 1 (1=enabled; 0=disabled) Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter request flag (1=active; 0=inactive) Unused bit, read as 0 INTC0 (0BH) Register
Bit No. 0 1 2, 3 4 5 6, 7
Label ETBI ERTI 3/4 TBF RTF 3/4
Function Controls the time base interrupt (1=enabled; 0:disabled) Controls the real time clock interrupt (1=enabled; 0:disabled) Unused bit, read as 0 Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read as 0 INTC1 (1EH) Register
Rev. 1.20
9
October 24, 2007
HT49RA0/HT49CA0
It is recommended that a program not use the CALL subroutine within the interrupt subroutine. Its because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. At this time, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. Oscillator Configuration An external resistor between OSC1 and VSS in needed and the resistance is about 12kW. The RC oscillator provides a 3% accuracy, the conditions are:
* VDD=2.0V~3.6V * Temp.= 0C ~ 50C * fSYS=4MHz
OSC1
RC
O s c illa to r
System Oscillator
LCD/RTC OSC Control Register Two bit in (1FH) are for controlling LCD and RTC OSC. Bit No. 0 1 2~7 Label RTCEN LCDEN 3/4 Function Controls RTC OSC enable (1=enabled; 0=disabled) Controls LCD enable (1=enabled; 0=disabled) Unused bit, read as 0 LCDC (1FH) Register LCDEN and RTCEN may decide LCD and RTC On/Off condition on normal operation. fS Clock Source fSYS/4 WDT OSC RTC OSC (WDT enable) RTC OSC (WDT disable) LCD/WDT Control Bits LCDEN, RTCEN=0, 0 LCD off, RTC off LCD off, RTC off LCD off, RTC on LCD off, RTC off LCDEN, RTCEN=0, 1 LCD off, RTC off LCD off, RTC off LCD off, RTC on LCD off, RTC on LCDEN, RTCEN=1, 0 LCD on, RTC off LCD on, RTC off LCD on, RTC on LCD on, RTC on LCDEN, RTCEN=1, 1 LCD on, RTC off LCD on, RTC off LCD on, RTC on LCD on, RTC on
Rev. 1.20
10
October 24, 2007
HT49RA0/HT49CA0
Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by option. But if the WDT is disabled, all executions related to the WDT lead to no operation. The WDT time-out period is as fS/216~fS/215. If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the HALT instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by an external logic. When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can stop the system clock. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the program counter and stack pointer are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from fS/212 to fS/215 selected by options. If time base time-out occurs, the related interrupt request flag
S y s te m C lo c k /4 O p tio n S e le c t fS D iv id e r P r e s c a le r CK R W D T C le a r T CK R T
(TBF; bit 4 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 10H occurs.
fS D iv id e r P r e s c a le r
O p tio n
O p tio n
LCD
D r iv e r ( fS /2
2
2
~ fS /2
9
8
)
T im e B a s e In te r r u p t (fS /2
12
B u z z e r (fS /2
~ fS /2
)
~ fS /2
15
)
Time Base Real Time Clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The real time clock time-out signal also can be applied to be a clock source of Timer/Event Counter for getting a longer time-out period. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 28* 29* 210* 211* 212 213 214 215
Note: * not recommended to be used
fS D iv id e r RT2 RT1 RT0 P r e s c a le r
8 to 1 M ux.
fS /2 ~ fS /2 R T C In te rru p t
8
15
Real Time Clock
RTC 32768H z OSC W DT 12kH z OSC
T im e - o u t R e s e t fS /2 16 ~ fS /2 15
Watchdog Timer Rev. 1.20 11 October 24, 2007
HT49RA0/HT49CA0
Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT OSC
Reset There are three ways in which reset may occur.
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time clock oscillator).
* All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared.
The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port B, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the program counter and Stack Pointer, and leaves the others at their original state. The port B wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port B can be independently selected to wake-up the device by option. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the HALT status, the system cannot be awaken using that interrupt. If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the Wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. When at HALT state and fS=fSYS/4, LCD and RTC will be turned off no matter the bit value of (LCDEN, RTCEN).
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and stack pointer and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition once the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different chip resets. Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT
TO 0 u 0 1 1 Note:
u means unchanged
To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state. Awaking from the HALT state, the SST delay is added. An extra SST delay is added during the power-up period and any wakeup from the HALT may enable only the SST delay. The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler, Divider WDT, RTC, Time base 000H Disabled Cleared Cleared. After master reset, WDT starts counting
Timer/Event Counter Off Input/output ports Stack Pointer Input mode Points to the top of the stack
Rev. 1.20
12
October 24, 2007
HT49RA0/HT49CA0
VDD RES S S T T im e - o u t C h ip R eset tS
ST
V
DD
V
DD
0 .0 1 m F 100kW RES 0 .1 m F 100kW RES 10kW 0 .1 m F H i-n o is e Reset C ir c u it
Reset Timing Chart
B a s ic Reset C ir c u it
W a rm R eset
H ALT W DT W DT T im e - o u t R eset E x te rn a l
Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit.
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
C o ld R eset
Reset Configuration
The states of the registers are summarized below: Register MP0 MP1 BP ACC Program Counter TBLP TBLH RTCC STATUS INTC0 TMR TMRC PA PB PC PCC INTC1 LCDC Note: Reset (Power-on) -xxx xxxx -xxx xxxx 0000 0000 xxxx xxxx 000H xxxx xxxx --xx xxxx --00 0111 --00 xxxx -000 0000 xxxx xxxx 0000 1--1111 1111 1111 1111 ---- ---1 ---- ---1 --00 --00 ---- --11 * refers to warm reset u means unchanged x means unknown - means unimplemented WDT Time-out RES Reset (Normal Operation) (Normal Operation) -uuu uuuu -uuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu --uu uuuu --00 0111 --1u uuuu -000 0000 xxxx xxxx 0000 1--1111 1111 1111 1111 ---- ---1 ---- ---1 --00 --00 ---- --11 -uuu uuuu -uuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu --uu uuuu --00 0111 --uu uuuu -000 0000 xxxx xxxx 0000 1--1111 1111 1111 1111 ---- ---1 ---- ---1 --00 --00 ---- --11 RES Reset (HALT) -uuu uuuu -uuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu --uu uuuu --00 0111 --01 uuuu -000 0000 xxxx xxxx 0000 1--1111 1111 1111 1111 ---- ---1 ---- ---1 --00 --00 ---- --11 WDT Time-out (HALT)* -uuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu --uu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu ---- ---u ---- ---u --uu --uu ---- --uu
Rev. 1.20
13
October 24, 2007
HT49RA0/HT49CA0
Timer/Event Counter One timer/event counters are implemented in the devices. It contains an 8-bit programmable count-up counter. The timer/event counter clock source may come from the system clock or system clock/4 or RTC time-out signal or external source. System clock source or system clock/4 is selected by option. Using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are two registers related to the timer/event counter, i.e., TMR (0DH) and TMRC (0EH). There are also two physical registers are mapped to TMR location; writing TMR places the starting value in the timer/event counter preload register, while reading it yields the contents of the timer/event counter. TMRC is timer/event counter control register used to define some options. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement Bit No. 0~2 3 4 5 Label 3/4 TE TON TS Unused bit, read as 0 To define the TMR active edge of timer/event counter (0=active on low to high; 1=active on high to low) To enable/disable timer counting (0=disabled; 1=enabled) 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0=RTC outputs; 1= system clock or system clock/4) To define the operating mode (TM1, TM0) 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMRC (0EH) Register
S y s te m S y s te m C lo c k C lo c k /4
mode can be used to count the high or low level duration of the external signal (TMR), and the counting is based on the internal selected clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (TF;bit 6 of INTC0). In the pulse width measurement mode with the values of the TON and TE bit equal to one, after the TMR has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR returns to the original level and resets the TON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be made until the TON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting according not to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues an interrupt request, as in the other two modes, i.e., event and timer modes.
Function
6 7
TM0 TM1
O p tio n S e le c t M U X
R T C In te rru p t TS TM R TE TM 1 TM 0 TON
D a ta b u s TM 1 TM 0 T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
T im e r /E v e n t C o u n te r
O v e r flo w T o In te rru p t
Timer/Event Counter Rev. 1.20 14 October 24, 2007
HT49RA0/HT49CA0
To enable the counting operation, the Timer ON bit (TON: bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON is automatically cleared after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI disables the related interrupt service. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR) is read, the clock is blocked to avoid errors. As this may results in a counting error, blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR register first, then turn on the related timer/event counter for proper operation. Because the initial value of TMR is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredicatable result. After this procedure, the timer/event function can be operated normally. Carrier Generator The HT49RA0/HT49CA0 provides a carrier output which shares the pin with PC0. It can be selected to be a carrier output (REM) or level output pin (PC0) by code option. If the carrier output option is selected, setting PC0=1 to enable carrier output and setting PC0=0 to disable it at low level output. The clock source of the carrier is implemented by instruction clock (system clock divided by 4) and processed by a frequency divider to yield various carry frequency. Carry Frequency= Clock Source m 2n
where m=2 or 3 and n=0~3, both are selected by code option. If m=2, the duty cycle of the carrier output is 1/2 duty. If m=3, the duty cycle of the carrier output can be 1/2 duty or 1/3 duty also determined by code option (with the exception of n=0). Detailed selection of the carrier duty is shown below: m2n 2, 4, 8, 16 3 6, 12, 24 1/2 1/3 1/2 or 1/3 Duty Cycle
The following table shows examples of carrier frequency selection. fSYS 455kHz 56.9kHz 1/2 only 2 fCARRIER 37.92kHz Duty 1/3 only m2n 3
F r e q u e n c y D iv id e r C lo c k S o u r c e ( S y s te m C lo c k /4 ) 3 - b it C o u n te r 1 /2 o r 1 /3 d u ty 1 /2 C o d e O p tio n 1 /3 C a r r ie r D u ty S e le c t REM1
Carrier/Level Output
Rev. 1.20
15
October 24, 2007
HT49RA0/HT49CA0
Input/Output Ports There are an 8-bit bidirectional input/output port, a 8-bit input port and one-bit input/output port in the HT49RA0/HT49CA0, labeled as PA, PB and PC which are mapped to [12H], [14H], [16H] of the RAM respectively. Each bit of PA can be selected as NMOS output or Schmitt trigger with pull-high resistor by software instruction. PB0~PB7 can only be used for input operation (Schmitt trigger with pull-high resistors). PC is only one-bit input/output port shares the pin with carrier output. When PA, PB and PC for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m] (m=12H or 14H). For PA and PC output operation, all data are latched and remain unchanged until the output latch is rewritten. When the PA is used for input operation, it should be noted that before reading data from pads, a 1 should be written to the related bits to disable the NMOS device. That is, the instruction SET [m].i (i=0~7 for PA) is executed first to disable related NMOS device, and then MOV A, [m] to get stable data. After chip reset, PA, PB and PC remain at a high level input line. Each bit of PA and PC output latches can be set or cleared by the SET [m].i and CLR [m].i (m=12H or 16H) instructions respectively. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m], CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each line of PB has a wake-up capability to the device by code option. The highest seven bits of PC are not physically implemented, on reading them a 0 is returned and writing results in a no-operation.
V
DD
W eak P u ll- u p D a ta B u s D Q CK S Q W r ite C h ip R e s e t R e a d I/O PA0~PA7
PA Input/Output Ports
V
DD
W eak P u ll- u p
D a ta B u s R e a d I/O S y s te m W a k e -u p W a k e - u p O p tio n
PB0~PB7
IN T 0 fo r P B 0 IN T 1 fo r P B 1 T M R fo r P B 2
PB Input Ports
Rev. 1.20
16
October 24, 2007
HT49RA0/HT49CA0
V C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r P C 0 /R E M D a ta B it Q D CK S M REM1 M U X R e a d D a ta R e g is te r U X S e le c t Q Q P u ll- H ig h O p tio n
DD
W r ite D a ta R e g is te r
P C 0 /R E M
PC Input/Output Ports
LCD Display Memory The devices provides an area of embedded data memory for LCD display. This area is located from 40H to 54H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as 1, any data written into 40H~54H will effect the LCD display. When the BP is cleared to 0, any data written into 40H~54H means to access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the devices.
COM 0 1 2 2 3 3 40H 41H 42H 43H 52H 53H 54H B it 0 1
LCD Driver Output The output number of the LCD driver device can be 212, 213 or 204 by option. The bias type LCD driver can be C type only. A capacitor mounted between C1 and C2 pins is needed. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins. All the capacitance of capacitors used for LCD bias generator is suggested to use the 0.1mF. The relationships between LCD bias types, bias levels and V1 and V2 connection are listed in the table. Bias Level 1/2 1/3 Bias Type C C C1/C2 0.1mF 0.1mF V1 x 0.1mF V2 0.1mF 0.1mF VLCD VLCD VLCD
There is a clock source needed for LCD driver. The LCD clock source comes from the general purpose prescaler and is decided by code options. The LCD clock frequency should be selected as near to 4kHz either from 32768 RTC or WDT or fSYS/4 clock source. The options of LCD clock frequency are listed in the following table. fS Clock Source WDT Oscillator LCD Clock Selection WDT/22 RTC/23 fSYS/24~fSYS/210
SEGMENT
0
1
2
3
18
19
20
RTC Oscillator fSYS/4
Display Memory
Rev. 1.20
17
October 24, 2007
HT49RA0/HT49CA0
D u r in g a R e s e t P u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts VA VB VSS VA VB VSS
N o r m a l O p e r a tio n M o d e COM0 COM1 COM2 L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e lig h te d HALT M ode C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D V A = V L C D , V B = V L C D x 1 /2 is u s e d . VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS S S S S S VA VA
S S S S S S
VB VSS VA VB VSS
LCD Driver Output (1/3 Duty, 1/2 Bias, C Type)
Rev. 1.20
18
October 24, 2007
HT49RA0/HT49CA0
VA COM0 VB VC VSS VA VB COM1 VC VSS VA COM2 VB VC VSS VA VB COM3 VC VSS VA L C D s e g m e n ts O N C O M 2 s id e lig h te d VB VC VSS N o te : V A = V L C D x 1 .5 , V B = V L C D , V C = V L C D x 1 /2
LCD Driver Output (1/4 Duty, 1/3 Bias, C Type)
Rev. 1.20
19
October 24, 2007
HT49RA0/HT49CA0
Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled. The RTCC register definitions are listed below. Bit No. 0~2 3 4 5 6, 7 Label RT0~RT2 LVDC* QOSC LVDO 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillating 0/1: quickly/slowly start LVD detection output (1/0) 1: low voltage detected, read only Unused bit, read as 0 RTCC (09H) Register Once the LVD function is enabled the reference generator should be enabled; otherwise the reference generator is controlled by LVR code option. The relationship among LVR and LVD options and LVDC are as shown. LVDC can read/write, LVDO is read only. LVD Enable Enable Enable Enable Disable Disable LVR Enable Enable Disable Disable Enable Disable LVDC On Off On Off X X VREF Generator Enable Enable Enable Disable Enable Disable LVR Comparator Enable Enable Disable Disable Enable Disable LVD Comparator Enable Disable Enable Disable Disable Disable
Rev. 1.20
20
October 24, 2007
HT49RA0/HT49CA0
The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as might happen when changing a battery, the LVR will automatically reset the device internally. During a HALT state, LVR is disabled. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) state must exists for
The relationship between VDD and VLVR is shown below.
VDD 3 .6 V
V 2 .0 V
LVR
more than 1ms, while the other circuits remain in their original state. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function.
* The LVR uses the OR function with the power-on re-
0 .9 V
set signal to perform a chip reset.
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
V 3 .6 V
DD
V
LVR
L V R D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1 To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2 Low voltage state has to be maintained for over 1ms, then after a 1ms delay the device enters the reset mode.
Rev. 1.20
21
October 24, 2007
HT49RA0/HT49CA0
Options The following shows the options in the devices. All these options should be defined in order to ensure proper system functioning. Item I/O Options 1 2 3 PB0~PB7: wake-up enable or disable (bit option) PC0: CMOS output or carrier output (bit option) PC0: Pull-high enable or disable (bit option) Options
LCD Options 4 5 6 7 8 LCD clock: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28 LCD duty: 1/2, 1/3, 1/4 LCD bias: 1/2, 1/3 LCD segment 12~15 output or CMOS output(Nibble Option) LCD segment 16~19 output or CMOS output(Nibble Option)
Interrupt Options 9 10 11 12 INT0 function: enable or disable Triggering edge: rising, falling or both INT1 function: enable or disable Triggering edge: rising, falling or both
Oscillator Options 13 fS internal clock source: RTC oscillator, WDT oscillator or fSYS/4
Timer Options 14 Timer/Event Counter clock source: fSYS or fSYS/4 Time Base division ratio: fS/212, fS/213, fS/214, fS/215
Time Base Options 15
Watchdog Options 16 17 WDT enable or disable CLRWDT instructions: 1 or 2 instructions
LVD/LVR Options 18 19 Low Voltage Detect: enable or disable LVR function: enable or disable
Carrier Options 20 21 22 23 Carrier duty: 1/2 duty or 1/3 duty Carrier frequency: fSYS/8, fSYS/16, fSYS/32, fSYS/64 for 1/2 duty cycle Carrier frequency: fSYS/12, 1/3 duty cycle Carrier frequency: fSYS/24, fSYS/48, fSYS/96 for 1/2 duty or 1/3 duty cycle
Rev. 1.20
22
October 24, 2007
HT49RA0/HT49CA0
Application Circuits
V
DD
VDD Reset C ir c u it RES 0 .1 m F VSS OSC C ir c u it PA0~PA7 P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R PB3~PB7 OSC1 R P C 0 /R E M OSC1 3 2 7 6 8 H z C ry s ta l S y s te m O s c illa to r O S C 1 L e ft U n c o n n e c te d V
DD
100kW 0 .1 m F
470pF
OSC
OSC1
RC RO
SC
S y s te m =12kW
O s c illa to r
OSC3
OSC4 H T 4 9 R A 0 /H T 4 9 C A 0 OSC
C ir c u it
Note:
1. Reset circuit The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 2. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information.
Rev. 1.20
23
October 24, 2007
HT49RA0/HT49CA0
Example
PA1 PA0 PB3 PB2 PB1 PB0 V
DD
PA2 PA3 PA4 PA5 PB7 PB6
VDD Reset C ir c u it RES 0 .1 m F VSS
PB5 PB4
100kW 0 .1 m F
VLC D
LCD
P o w e r S u p p ly
CO M 0~CO M 2 C O M 3 /S E G 2 0 SEG 0~SEG 19
LCD PANEL
33W 1W Vbat 220W ~1kW 100mF
VDD
C1 0 .1 m F C2
V1 P C 0 /R E M 0 .1 m F
V2 OSC C ir c u it OSC1 0 .1 m F
H T 4 9 R A 0 /H T 4 9 C A 0
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Instruction Set
Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.20 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 28 October 24, 2007
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
52-pin QFP (1414) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.3 13.9 17.3 13.9 3/4 3/4 2.5 3/4 3/4 0.73 0.1 0 Nom. 3/4 3/4 3/4 3/4 1 0.4 3/4 3/4 0.1 3/4 3/4 3/4 Max. 17.5 14.1 17.5 14.1 3/4 3/4 3.1 3.4 3/4 1.03 0.2 7
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October 24, 2007
HT49RA0/HT49CA0
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
39
October 24, 2007


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